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ADT7468
SERIAL BUS INTERFACE
On PCs and servers, control of the ADT7468 is carried out
using the serial system management bus (SMBus). The
ADT7468 is connected to this bus as a slave device, under the
control of a master controller, which is usually (but not
necessarily) the ICH.
The ADT7468 has a fixed 7-bit serial bus address of 0101110 or
0x2E. The read/write bit must be added to get the 8-bit address
(01011100 or 0x5C). Data is sent over the serial bus in
sequences of nine clock pulses: eight bits of data followed by an
acknowledge bit from the slave device. Transitions on the data
line must occur during the low period of the clock signal and
remain stable during the high period, because a low-to-high
transition might be interpreted as a stop signal when the clock
is high. The number of data bytes that can be transmitted over
the serial bus in a single read or write operation is limited only
following functions. To write data to one of the device data
registers or read data from it, the address pointer register must
be set so that the correct data register is addressed, then data
can be written into that register or read from it. The first byte of
a write operation always contains an address that is stored in
the address pointer register. If data is to be written to the device,
then the write operation contains a second data byte that is
written to the register selected by the address pointer register.
This write operation is illustrated in Figure 16. The device
address is sent over the bus, and then R/W is set to 0. This is
followed by two data bytes. The first data byte is the address of
the internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.
When reading data from a register, there are two possibilities:
by what the master and slave devices can handle.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition. In
read mode, the master device overrides the acknowledge bit by
pulling the data line high during the low period before the
ninth clock pulse. This is known as a no acknowledge. The
master then takes the data line low during the low period before
the 10th clock pulse, and then high during the 10th clock pulse
to assert a stop condition.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
In the ADT7468, write operations contain either one or two
bytes, and read operations contain one byte and perform the
?
?
If the ADT7468’s address pointer register value is unknown
or not the desired value, it must be set to the correct value
before data can be read from the desired data register. This
is done by performing a write to the ADT7468, but only
the data byte containing the register address is sent, since
no data is written to the register. This is shown in
Figure 17.
A read operation is then performed consisting of the serial
bus address, R/W, bit set to 1, followed by the data byte
read from the data register. This is shown in Figure 18.
If the address pointer register is known to be at the desired
address, data can be read from the corresponding data
register without first writing to the address pointer register,
as shown in Figure 18
1
9
1
9
SCL
SDA
0
1
0
1
1
1
0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
ACK. BY
ADT7468
FRAME 2
ACK. BY
ADT7468
SERIAL BUS ADDRESS BYTE
SCL (CONTINUED)
1
ADDRESS POINTER REGISTER BYTE
9
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
STOP BY
FRAME 3
ADT7468
MASTER
DATA BYTE
Figure 16. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
Rev. 3 | Page 12 of 81 | www.onsemi.com
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